1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and, more particularly, to the formation of metallization layers in contacts and local interconnects of such devices, e.g., MOS transistor structures.
2. Description of the Related Art
The fabrication of integrated circuit devices involves numerous processing steps. One important aspect in the manufacturing procedure is to provide low resistivity connections between the various components of the integrated circuit devices, e.g., between the MOSFETs or bipolar devices of an integrated circuit (interconnects) as well as to components of a single device (local interconnect) or junctions to the semiconductor material (contacts). The latter type of electrical connections generally requires the formation of openings in a dielectric layer covering the wafer surface by means of an anisotropic etching process. Due to the demand of decreasing circuit sizes, the openings have substantially vertical sidewalls in order to save space. The openings are filled by a contact metal, such as tungsten, typically through use of a chemical vapor deposition process ("CVD"). However, difficulties in the deposition process arise as the adhesion of the metal to the sidewalls of the opening in the dielectric material is rather poor. Therefore, forming a thin adhesion layer, for example, a titanium layer, covering the sidewalls and the bottom of the opening has become a standard procedure.
A further issue which is steadily gaining in importance, particularly in view of the ever decreasing circuitry dimensions, is the problem of electromigration, i.e., material transport of the metallization layer caused by the flow of an electrical current. Electromigration may lead to discontinuities in the metallization layer and result in the failure of the electrical connection. In addition, the resistivity of the metal increases when electromigration occurs since voids appear within the metal and thereby reduce the area of the metal through which the charge carriers can pass. While tungsten is presently preferred to aluminum for formation of contact plugs because it is less susceptible to electromigration, there is still a need for improvement of the mechanical stability and the electrical characteristics of such contact plugs.
One illustrative prior art process for forming a contact plug will be explained with reference to FIG. 1. FIG. 1 shows a cross-section of a semiconductor topography representing an illustrative MOS transistor fabricated by prior art processing techniques. A composite barrier layer (adhesion layer) 15 composed of a titanium layer and a titanium nitride layer separates a local interconnect dielectric material 19 from a local interconnect metal plug 17. An illustrative cobalt silicide layer 9 is formed above the semiconducting substrate. The cobalt silicide layer 9 and the plug 17 are separated by a barrier layer 15. An active junction 3 is electrically connected to the plug 17 through the cobalt silicide layer 9. Two structures 3, as described above, representing the drain and source areas, respectively, are separated by the gate area consisting of a gate oxide 7 on which a polysilicon layer 6 is formed. A cobalt silicide layer 8 is also formed on top of the polysilicon layer 6. The side-walls of the gate stack are surrounded by a spacer material 11. The top of the gate stack is covered by the dielectric material 19.
The following is a brief description of one typical prior art process for making the structure as illustrated in FIG. 1. After the formation of a cobalt silicide layer 8, 9 by conventional silicide processing, a silicon-nitride etch-stop layer (not shown) of about 500-1500 .ANG. (50-150 nm) is formed. Subsequently, a dielectric material 19, which may be formed from tetraethoxysilane (TEOS), doped or undoped, and possibly comprising an antireflecting coating is deposited. The dielectric material 19 may have a typical thickness of about 7000-8000 .ANG. (700-800 nm). After the deposition of the dielectric material 19, and the completion of a chemical mechanical polishing step, a lithography step is carried out, wherein optical proximity corrections may be employed, depending on the feature size. Next, openings 2 are formed in the dielectric material 19 by an etching process, wherein the etching process stops on the etch-stop layer. In a further processing step, the etch-stop layer is removed from the bottom of the openings 2 by a selective etching process. Due to limited selectivity of this latter etching step with respect to the cobalt silicide layer 9, and the necessity to over-etch in order to avoid open contacts, the cobalt silicide layer 9 under 15 the openings 2 suffers a loss of material, resulting in an increased contact resistance of the remaining cobalt silicide layer 9 as compared to the initial cobalt silicide layer. After etching and removing the etch-stop layer, the barrier layer 15, typically consisting of titanium/titanium-nitride bilayer, is deposited. The openings 2 are then filled in with a metal, such as tungsten, by a chemical vapor deposition process, thereby forming a plug 17. In a further processing step, the excess tungsten and the excess barrier layer 15 on the top surface are removed by, for example, a chemical mechanical polishing operation.
As mentioned above, the barrier layer 15 (adhesion layer) is desirable to attain a sufficient adhesion of the metal, e.g., tungsten, on the sidewalls of the trenches during the deposition process. Moreover, the barrier layer 15 serves as a diffusion barrier in order to avoid an undesired interaction of the tungsten with the underlying layers, in particular, interaction with the doped area of the active junctions 3.
As a result, when contacts are opened and local interconnect trenches are formed, the cobalt suicide (CoSi.sub.2) layer 9 is partially removed in the area beneath the openings 2 due to both the limited selectivity of the etch process, and the necessity to over-etch in order to avoid open electrical contacts. This problem is aggravated as shallow junctions in MOSFET devices require very thin silicide layers, due to the demand of decreased circuit dimensions. Therefore, the loss of even portions of the initial, thin silicide layer 9 during the etching process may strongly affect the quality of the remaining silicide layer, in particular with respect to its electrical resistance. Accordingly, the contact resistance of the remaining cobalt silicide (CoSi.sub.2) layer 9 is increased, thus leading to an increased contact resistance to the underlying junction. In view of the above mentioned problem, a need exists for an integrated semiconductor device having a metallization comprising a metal silicide layer without the aforementioned process-related increase in contact resistance. Moreover, the material used for metallization layers should exhibit mechanical as well as chemical stability during the various processing steps.
The present invention is directed to a method for solving, or at least reducing the effects of, some or all of the aforementioned problems.